A Novel Power-Hardware-in-the-Loop Interface Method for Grid-Forming Inverter Systems: Preprint

Soham Chakraborty, Jaesang Park, Govind Saraswat, Toby Meyers, Jing Wang, Soumya Tiwari, Atif Maqsood, Apurva Somani, Murti Salapaka

Research output: Contribution to conferencePaper

Abstract

Power Hardware-in-the-Loop (PHIL) simulation of grid-forming (GFM) inverter systems facilitates the testing of drastic scenarios like on-grid to off-grid transition, islanded microgrid operation without stiff grid etc. To the authors best knowledge, most of studies in literature are focused on PHIL simulation for grid-following inverter systems and only few studies are focused on GFM inverters and those are challenging and problematic especially for high-power applications. In this article, a novel PHIL simulation platform is proposed that enables interfacing of high-power GFM inverter systems. It proposes the concept of a virtual GFM inverter as a part of the proposed PHIL interface for GFM inverter. This addition of virtual GFM inverter in the PHIL interface expands the conventional Ideal Transformer Model (ITM) method and enables it to overcome the issues of instability of existing ITM methods. In the validation stage, a PHIL experiment is conducted on a 3-phase 480 V, 125 kVA GFM inverter system with proposed interfacing method. The results corroborates the fact that the proposed PHIL simulation method performs well and stable for GFM inverter system.
Original languageAmerican English
Number of pages9
StatePublished - 2022
Event48th Annual Conference of the IEEE Industrial Electronics Society (IECON) - Brussels, Belgium
Duration: 17 Oct 202220 Oct 2022

Conference

Conference48th Annual Conference of the IEEE Industrial Electronics Society (IECON)
CityBrussels, Belgium
Period17/10/2220/10/22

Bibliographical note

See NREL/CP-5D00-85137 for paper as published in proceedings

NREL Publication Number

  • NREL/CP-5D00-82885

Keywords

  • grid-forming inverters
  • power hardware-in-the-loop (PHIL) simulation
  • stability

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