Characterization of Engineered Pinholes in Dielectric Stacks of High-Performance Poly-Silicon Passivating Contacts

Harvey Guthrey, Caroline Lima Salles, William Nemeth, Sumit Agarwal, David Young, Paul Stradins

Research output: NRELPoster


Passivating contact structures are expected to be implemented in > 50 % of industrially manufactured silicon photovoltaics produced over the next decade. One type of passivating contact utilizes a c-Si/dielectric/doped poly-Si layer stack. In cases where the dielectric layer/s are thick enough to impede tunneling of charge carriers, it was shown that disruptions (pinholes) in the dielectric are required to facilitate transport.[1] Pinholes in SiOx layers have typically been formed via high temperature annealing that allows localized breakup of this layer. This approach has drawbacks; 1) high temperature annealing increases cost and 2) pinhole formation is sensitive to both the SiOx thickness and wafer surface morphology making control of density and dimensions difficult. Recently, an alternative method of pinhole formation relying on metal assisted chemical etching (MACE) was shown to allow control over pinhole areal densities.[2] Such control is critical as both the density and dimensions of the pinholes determine saturation current density and contact resistivity. The contacts formed with the MACE process are known as polysilicon on locally etched oxide or PLEO and also result in low saturation current densities and low contact resistivity due to SiOx passivation and engineered pinhole enabled charge carrier transport, respectively. Photovoltaic devices with efficiencies greater than 20 % have recently been produced with these contacts, demonstrating the viability of contacts with engineered pinholes. Experimentally, preferential local collection of excess charge carriers has been observed and definitively connected to thermally induced pinholes in thick SiOx layers within c-Si/SiOx/poly-Si contact structures.[3] Recent work has shown that enhanced local collection of excess carriers can result from enhanced diffusion of dopants through pinholes in SiOx layers.[4] This study was restricted to simulation and characterization of poly-Si with the same dopant type as the c-Si substrates. In this work we focus our analysis on boron doped poly-Si with different stacks of dielectric layers (PLEO and PLENO where the N refers to a SiNy layer on top of the SiOx) on n-type crystalline silicon. This provides insight into how engineered pinholes affect charge collection across the p-n junction. Like previous observations of locally enhanced carrier transport through thermally induced pinholes, the EBIC images in Figure 1 shows that engineered pinholes in PLENO (1a) and PLEO (1b) also exhibit locally enhanced carrier transport at pinhole locations (bright spots in the images). We will also present detailed correlative nanoscale structural and chemical analysis using TEM imaging and EELS analysis with sample preparation guided by EBIC imaging. This allows us to connect the density and dimensions of engineered pinholes with charge carrier transport and measured photovoltaic device parameters. Our findings will accelerate the adoption of PLEO and PLENO contacts in industrially manufactured photovoltaic devices.
Original languageAmerican English
StatePublished - 2022

Publication series

NamePresented at the 33rd International Photovoltaic Science and Engineering Conference (PVSEC-33), 13-17 November 2022, Nagoya, Japan

NREL Publication Number

  • NREL/PO-5K00-84482


  • EBIC
  • passivating contacts
  • silicon characterization
  • silicon photovoltaics


Dive into the research topics of 'Characterization of Engineered Pinholes in Dielectric Stacks of High-Performance Poly-Silicon Passivating Contacts'. Together they form a unique fingerprint.

Cite this