Development of Application Function Blocks for Power-Hardware-in-the-Loop Testing of Grid-Connected Inverters

Jing Wang; John Fossum; Kumaraguru Prabakar; Annabelle Pratt; Murali Baggu

doi:10.1109/PEDG.2018.8447590

Development of Application Function Blocks for Power-Hardware-in-the-Loop Testing of Grid-Connected Inverters

Jing Wang, John Fossum, Kumaraguru Prabakar, Annabelle Pratt, Murali Baggu

Research output: Contribution to conference › Paper › peer-review

5 Scopus Citations

Abstract

This paper presents standard Application Function Blocks (AFBs) for Power-Hardware-In-the-Loop (PHIL) testing of grid-connected inverters. The main objective is to develop standard AFBs that can be used as an interface between PHIL simulation and hardware. A critical feature of the AFBs is the ability to be reused and reconfigured with minimal effort for various PHIL tests. The PHIL interface includes five AFBs: power amplifier protection, PHIL interfacing compensation, analog output conditioning, analog input conditioning, and device under test (DUT) energy generation model. The design and development of each AFB is presented in detail for PHIL researchers. A test procedure is provided to aid in replicating the work and to guarantee safe operation. Experimental results of testing the battery and PV inverters demonstrate the effectiveness of the developed AFBs. A discussion on the reusability and reconfigurability of AFBs is presented, showing the value of using standard AFBs for accelerating the PHIL test.

Original language	American English
Number of pages	8
DOIs	https://doi.org/10.1109/PEDG.2018.8447590 https://doi.org/10.1109/PEDG.2018.8447590
State	Published - 27 Aug 2018
Event	9th IEEE International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2018 - Charlotte, United States Duration: 25 Jun 2018 → 28 Jun 2018

Conference

Conference	9th IEEE International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2018
Country/Territory	United States
City	Charlotte
Period	25/06/18 → 28/06/18

Bibliographical note

See NREL/CP-5D00-70691 for preprint

NREL Publication Number

NREL/CP-5D00-72614

Keywords

application function block
grid-connected inverter
power-hardware-in-the-loop (PHIL)
test procedure

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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Cite this

Wang, J., Fossum, J., Prabakar, K., Pratt, A., & Baggu, M. (2018). Development of Application Function Blocks for Power-Hardware-in-the-Loop Testing of Grid-Connected Inverters. Paper presented at 9th IEEE International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2018, Charlotte, United States. https://doi.org/10.1109/PEDG.2018.8447590, https://doi.org/10.1109/PEDG.2018.8447590

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title = "Development of Application Function Blocks for Power-Hardware-in-the-Loop Testing of Grid-Connected Inverters",

abstract = "This paper presents standard Application Function Blocks (AFBs) for Power-Hardware-In-the-Loop (PHIL) testing of grid-connected inverters. The main objective is to develop standard AFBs that can be used as an interface between PHIL simulation and hardware. A critical feature of the AFBs is the ability to be reused and reconfigured with minimal effort for various PHIL tests. The PHIL interface includes five AFBs: power amplifier protection, PHIL interfacing compensation, analog output conditioning, analog input conditioning, and device under test (DUT) energy generation model. The design and development of each AFB is presented in detail for PHIL researchers. A test procedure is provided to aid in replicating the work and to guarantee safe operation. Experimental results of testing the battery and PV inverters demonstrate the effectiveness of the developed AFBs. A discussion on the reusability and reconfigurability of AFBs is presented, showing the value of using standard AFBs for accelerating the PHIL test.",

keywords = "application function block, grid-connected inverter, power-hardware-in-the-loop (PHIL), test procedure",

author = "Jing Wang and John Fossum and Kumaraguru Prabakar and Annabelle Pratt and Murali Baggu",

note = "See NREL/CP-5D00-70691 for preprint; 9th IEEE International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2018 ; Conference date: 25-06-2018 Through 28-06-2018",

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doi = "10.1109/PEDG.2018.8447590",

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Wang, J, Fossum, J, Prabakar, K , Pratt, A & Baggu, M 2018, 'Development of Application Function Blocks for Power-Hardware-in-the-Loop Testing of Grid-Connected Inverters', Paper presented at 9th IEEE International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2018, Charlotte, United States, 25/06/18 - 28/06/18. https://doi.org/10.1109/PEDG.2018.8447590, https://doi.org/10.1109/PEDG.2018.8447590

Development of Application Function Blocks for Power-Hardware-in-the-Loop Testing of Grid-Connected Inverters. / Wang, Jing; Fossum, John; Prabakar, Kumaraguru et al.
2018. Paper presented at 9th IEEE International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2018, Charlotte, United States.

Research output: Contribution to conference › Paper › peer-review

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AU - Pratt, Annabelle

AU - Baggu, Murali

N1 - See NREL/CP-5D00-70691 for preprint

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N2 - This paper presents standard Application Function Blocks (AFBs) for Power-Hardware-In-the-Loop (PHIL) testing of grid-connected inverters. The main objective is to develop standard AFBs that can be used as an interface between PHIL simulation and hardware. A critical feature of the AFBs is the ability to be reused and reconfigured with minimal effort for various PHIL tests. The PHIL interface includes five AFBs: power amplifier protection, PHIL interfacing compensation, analog output conditioning, analog input conditioning, and device under test (DUT) energy generation model. The design and development of each AFB is presented in detail for PHIL researchers. A test procedure is provided to aid in replicating the work and to guarantee safe operation. Experimental results of testing the battery and PV inverters demonstrate the effectiveness of the developed AFBs. A discussion on the reusability and reconfigurability of AFBs is presented, showing the value of using standard AFBs for accelerating the PHIL test.

AB - This paper presents standard Application Function Blocks (AFBs) for Power-Hardware-In-the-Loop (PHIL) testing of grid-connected inverters. The main objective is to develop standard AFBs that can be used as an interface between PHIL simulation and hardware. A critical feature of the AFBs is the ability to be reused and reconfigured with minimal effort for various PHIL tests. The PHIL interface includes five AFBs: power amplifier protection, PHIL interfacing compensation, analog output conditioning, analog input conditioning, and device under test (DUT) energy generation model. The design and development of each AFB is presented in detail for PHIL researchers. A test procedure is provided to aid in replicating the work and to guarantee safe operation. Experimental results of testing the battery and PV inverters demonstrate the effectiveness of the developed AFBs. A discussion on the reusability and reconfigurability of AFBs is presented, showing the value of using standard AFBs for accelerating the PHIL test.

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Development of Application Function Blocks for Power-Hardware-in-the-Loop Testing of Grid-Connected Inverters

Abstract

Conference

Bibliographical note

NREL Publication Number

Keywords

UN SDGs

Access to Document

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Cite this