Device Architectures Having Engineered Stresses

Myles Steiner (Inventor)

Research output: Patent


The present disclosure relates to a method that includes depositing a spalling layer onto a surface that includes a substrate, depositing a device comprising a III-V material onto the spalling layer, resulting in the forming of a stack, and dividing the stack substantially at a plane positioned within the spalling layer to form a first portion that includes the substrate and a second portion that includes the PV device, where the spalling layer includes a first layer configured to provide a compressive stress and a second layer configured to provide a tensile stress, the first layer and the second layer form an interface, the dividing occurs as result of the interface, and the compressive stress and the tensile stress are strain-balanced so that a total strain within the spalling layer is approximately zero.
Original languageAmerican English
Patent number11,658,258 B2
Filing date23/05/23
StatePublished - 2023

NREL Publication Number

  • NREL/PT-5900-86381


  • III-V material
  • spalling layer
  • substrate
  • tensile stress


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