Abstract
Voltage loss is currently one of the biggest challenges facing cadmium telluride (CdTe) based photovoltaics. Determining the location(s) of major voltage loss within the device stack (e.g., front/back interface, grain boundaries) is therefore of primary interest. Here, we present a custom-built time-resolved photoluminescence system with two excitation wavelengths - 670 (standard) and 405 nm - to probe the device stack at depths of approximately 130 and 35 nm, respectively; their comparison helps differentiate interface and bulk contributions to carrier lifetime. We apply this system to examine the passivation effect of two significant recent advances in CdTe: the incorporation of Se to form graded CdSexTe1-x and the replacement of CdS with MgyZn1-yO. It is found that x = 0.2 Se is required to obtain lifetime improvements, primarily in the bulk. Additionally, evidence for trapping at the MgyZn1-yO/CdSexTe1-x interface was observed. This indicates further work is required to sufficiently passivate the front interface.
Original language | American English |
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Pages (from-to) | 309-315 |
Number of pages | 7 |
Journal | IEEE Journal of Photovoltaics |
Volume | 12 |
Issue number | 1 |
DOIs | |
State | Published - 1 Jan 2022 |
Bibliographical note
Publisher Copyright:© 2011-2012 IEEE.
NREL Publication Number
- NREL/JA-5K00-80301
Keywords
- Cadmium telluride (CdTe)
- CdSeTe
- Front interface
- MgZn O (MZO)
- Time-resolved photoluminescence (TRPL)