Effect of Silicon Oxide Thickness on Polysilicon Based Passivated Contacts for High-efficiency Crystalline Silicon Solar Cells

In this study, we have investigated the effect of SiO_x thickness (1–3 nm) on the performance of polycrystalline (poly) Si/SiO_x/monocrystalline Si (c-Si) passivated contacts. Our results show that for both n- and p-type contacts, there is an optimum SiO_x thickness of 1.4–1.6 nm for obtaining the highest implied open-circuit voltage (i-V_oc) values of ~739 and ~700 mV, respectively. For contacts with SiO_x thicker than 1.6 nm, the i-V_oc drops due to reduced field-effect passivation. We attribute this to the fact that a thicker SiO_x layer hinders the diffusion of both n- and p-type dopants into the c-Si wafer resulting in a junction that is very close to the c-Si/SiO_x interface, which increases carrier recombination most likely due to the presence of defects at this interface. The resistivity measured through the metal/poly-Si/SiO_x/c-Si stack is independent of SiO_x thickness up to 1.6 nm, and increases exponentially by several orders of magnitude with further increase in SiO_x thickness due to inefficient tunneling transport. Finally, the extent of metallization-induced degradation of the poly-Si/SiO_x/c-Si contacts is worst for the thinnest SiO_x investigated (~1 nm), and interestingly it is not completely mitigated even for a ~3 nm thick SiO_x.