Establishment of a PID Pass/Fail Test for Crystalline Silicon Modules by Examining Field Performance for Five Years: Preprint

In an experiment with five module designs and multiple replicas, it is found that crystalline silicon cell modules that can pass a criterion of less than 5 percent power degradation in stress test conditions of 60 degrees Celsius, 85 percent relative humidity (RH), 96 h, and nameplate-rated system voltage bias show no power degradation by potential induced degradation in the range of 4-6 years duration in the Florida, USA environment. This data suggests that this chamber stress level is useful as a pass/fail criterion for PID, and will help ensure against degradation by system voltage stress in Florida, or less stressful climates, for at least 5 years.