Excess Carrier Concentration in Silicon Devices and Wafers: How Bulk Properties are Expected to Accelerate Light and Elevated Temperature Degradation

Light and elevated temperature induced degradation (LeTID) is accelerated nearly linearly by the presence of excess carriers. It is therefore important to understand how excess carrier concentration (∆n) changes as a function of exposure conditions, materials properties, and sample structure. We simulate ∆n as a function of wafer thickness and bulk minority carrier lifetime (τ) in solar cells and wafers using SCAPS and Quokka3. We also derive closed-form analytic expressions. For wafers, there is a near-linear relationship between ∆n and τ or thickness, whereas for solar cells, ∆n in the bulk may become limited by rear surface recombination. Thus, LeTID may progress more quickly in wafers than in cells, with a stronger dependence on τ. When comparing experiments, observed degradation rates must be corrected between samples or conditions to account for differences in ∆n. This study demonstrates three tools to estimate the magnitude of such corrections, which can aid in the quantitative interpretation of LeTID data and performance predictions. While each tool yields similar results, there are advantages to each approach that must be weighed in terms of simplicity of inputs versus sophistication of treatment. Incomplete specification of back contact characteristics in commercial products is identified as an important contributor to uncertainty in expected LeTID rates. Graphical abstract: [Figure not available: see fulltext.].