Front/Back Poly-Si/SiO2 Passivated Contact Device with Voc > 720 mV

David Young; Vincenzo LaSalvia; William Nemeth; San Theingi; Abhijit Kale; Dawn Findley; Scott Atkins; Matthew Page; Pauls Stradins

doi:10.4229/35thEUPVSEC20182018-2AV.3.32

Front/Back Poly-Si/SiO2 Passivated Contact Device with Voc > 720 mV

David Young
, Vincenzo LaSalvia
, William Nemeth
, San Theingi
, Abhijit Kale
, Dawn Findley
, Scott Atkins
, Matthew Page
, Pauls Stradins

Chemistry and Nanoscience

Research output: Contribution to conference › Paper

Abstract

We report on front/back poly-Si/SiO2 passivated contact solar cells with iVoc > 735 mV and Voc > 720 mV. The devices were grown on n-Cz wafers using PECVD to deposit doped a-Si layers which were then annealed at 850 degrees C. Our best device has an efficiency of 21% which is limited by: (1) low current density from a large grid shadow loss and parasitic absorption in the front poly-Si:P layer; and (2) high series resistance from a high Al-poly-Si:P contact resistivity. We discuss the role of high temperature anneals throughout the process flow to preserve and improve the bulk lifetime of the n-Cz wafers.

Original language	American English
Pages	700-703
Number of pages	4
DOIs	https://doi.org/10.4229/35thEUPVSEC20182018-2AV.3.32
State	Published - 2018
Event	35th European Photovoltaic Solar Energy Conference and Exhibition - Brussels, Belgium Duration: 24 Sep 2018 → 27 Sep 2018

Conference

Conference	35th European Photovoltaic Solar Energy Conference and Exhibition
City	Brussels, Belgium
Period	24/09/18 → 27/09/18

NLR Publication Number

NREL/CP-5900-72446

Keywords

passivate contacts
solar cells
Tabula Rasa

Access to Document

10.4229/35thEUPVSEC20182018-2AV.3.32

Cite this

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title = "Front/Back Poly-Si/SiO2 Passivated Contact Device with Voc > 720 mV",

abstract = "We report on front/back poly-Si/SiO2 passivated contact solar cells with iVoc > 735 mV and Voc > 720 mV. The devices were grown on n-Cz wafers using PECVD to deposit doped a-Si layers which were then annealed at 850 degrees C. Our best device has an efficiency of 21\% which is limited by: (1) low current density from a large grid shadow loss and parasitic absorption in the front poly-Si:P layer; and (2) high series resistance from a high Al-poly-Si:P contact resistivity. We discuss the role of high temperature anneals throughout the process flow to preserve and improve the bulk lifetime of the n-Cz wafers.",

keywords = "passivate contacts, solar cells, Tabula Rasa",

author = "David Young and Vincenzo LaSalvia and William Nemeth and San Theingi and Abhijit Kale and Dawn Findley and Scott Atkins and Matthew Page and Pauls Stradins",

year = "2018",

doi = "10.4229/35thEUPVSEC20182018-2AV.3.32",

language = "American English",

pages = "700--703",

note = "35th European Photovoltaic Solar Energy Conference and Exhibition ; Conference date: 24-09-2018 Through 27-09-2018",

}

TY - CONF

T1 - Front/Back Poly-Si/SiO2 Passivated Contact Device with Voc > 720 mV

AU - Young, David

AU - LaSalvia, Vincenzo

AU - Nemeth, William

AU - Theingi, San

AU - Kale, Abhijit

AU - Findley, Dawn

AU - Atkins, Scott

AU - Page, Matthew

AU - Stradins, Pauls

PY - 2018

Y1 - 2018

N2 - We report on front/back poly-Si/SiO2 passivated contact solar cells with iVoc > 735 mV and Voc > 720 mV. The devices were grown on n-Cz wafers using PECVD to deposit doped a-Si layers which were then annealed at 850 degrees C. Our best device has an efficiency of 21% which is limited by: (1) low current density from a large grid shadow loss and parasitic absorption in the front poly-Si:P layer; and (2) high series resistance from a high Al-poly-Si:P contact resistivity. We discuss the role of high temperature anneals throughout the process flow to preserve and improve the bulk lifetime of the n-Cz wafers.

AB - We report on front/back poly-Si/SiO2 passivated contact solar cells with iVoc > 735 mV and Voc > 720 mV. The devices were grown on n-Cz wafers using PECVD to deposit doped a-Si layers which were then annealed at 850 degrees C. Our best device has an efficiency of 21% which is limited by: (1) low current density from a large grid shadow loss and parasitic absorption in the front poly-Si:P layer; and (2) high series resistance from a high Al-poly-Si:P contact resistivity. We discuss the role of high temperature anneals throughout the process flow to preserve and improve the bulk lifetime of the n-Cz wafers.

KW - passivate contacts

KW - solar cells

KW - Tabula Rasa

U2 - 10.4229/35thEUPVSEC20182018-2AV.3.32

DO - 10.4229/35thEUPVSEC20182018-2AV.3.32

M3 - Paper

SP - 700

EP - 703

T2 - 35th European Photovoltaic Solar Energy Conference and Exhibition

Y2 - 24 September 2018 through 27 September 2018

ER -

Front/Back Poly-Si/SiO2 Passivated Contact Device with Voc > 720 mV

Abstract

Conference

NLR Publication Number

Keywords

Access to Document

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Cite this