Impact of Accelerated Stress-Tests on SiC MOSFET Precursor Parameters

Douglas DeVoto; Joshua Major; Joseph Kozak; Khai Ngo

doi:10.1109/3DPEIM.2018.8525234

Impact of Accelerated Stress-Tests on SiC MOSFET Precursor Parameters

Douglas DeVoto, Joshua Major, Joseph Kozak, Khai Ngo

Center for Integrated Mobility Sciences

Virginia Tech

Research output: Contribution to conference › Paper › peer-review

19 Scopus Citations

Abstract

Integrating SiC power MOSFETs is very attractive for advancing power electronic system performance, yet the system reliability with new devices remains in question. This work presents an overview of accelerated lifetime tests and the packaging and semiconductor failure mechanisms they excite. The experiments explained here includes High Temperature Gate Bias (HTGB), Switching Cycling, Power Cycling, and Thermal Cycling. These experiments stress different failure mechanisms, that show degradation in different device parameters including, but not limited to, threshold voltage and on-resistance. These four experiments help illustrate the spectrum between device and package degradation that can be used to design more reliable power electronic circuits.

Original language	American English
Number of pages	5
DOIs	https://doi.org/10.1109/3DPEIM.2018.8525234 https://doi.org/10.1109/3DPEIM.2018.8525234
State	Published - 5 Nov 2018
Event	2nd International Symposium on 3D Power Electronics Integration and Manufacturing, 3D-PEIM 2018 - College Park, United States Duration: 25 Jun 2018 → 27 Jun 2018

Conference

Conference	2nd International Symposium on 3D Power Electronics Integration and Manufacturing, 3D-PEIM 2018
Country/Territory	United States
City	College Park
Period	25/06/18 → 27/06/18

Bibliographical note

See NREL/CP-5400-71331 for preprint

NREL Publication Number

NREL/CP-5400-73008

Keywords

Accelerated Testing
MOSFET
Reliability
Silicon Carbide

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Cite this

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title = "Impact of Accelerated Stress-Tests on SiC MOSFET Precursor Parameters",

abstract = "Integrating SiC power MOSFETs is very attractive for advancing power electronic system performance, yet the system reliability with new devices remains in question. This work presents an overview of accelerated lifetime tests and the packaging and semiconductor failure mechanisms they excite. The experiments explained here includes High Temperature Gate Bias (HTGB), Switching Cycling, Power Cycling, and Thermal Cycling. These experiments stress different failure mechanisms, that show degradation in different device parameters including, but not limited to, threshold voltage and on-resistance. These four experiments help illustrate the spectrum between device and package degradation that can be used to design more reliable power electronic circuits.",

keywords = "Accelerated Testing, MOSFET, Reliability, Silicon Carbide",

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DeVoto, D , Major, J, Kozak, J & Ngo, K 2018, 'Impact of Accelerated Stress-Tests on SiC MOSFET Precursor Parameters', Paper presented at 2nd International Symposium on 3D Power Electronics Integration and Manufacturing, 3D-PEIM 2018, College Park, United States, 25/06/18 - 27/06/18. https://doi.org/10.1109/3DPEIM.2018.8525234, https://doi.org/10.1109/3DPEIM.2018.8525234

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AU - DeVoto, Douglas

AU - Major, Joshua

AU - Kozak, Joseph

AU - Ngo, Khai

N1 - See NREL/CP-5400-71331 for preprint

PY - 2018/11/5

Y1 - 2018/11/5

N2 - Integrating SiC power MOSFETs is very attractive for advancing power electronic system performance, yet the system reliability with new devices remains in question. This work presents an overview of accelerated lifetime tests and the packaging and semiconductor failure mechanisms they excite. The experiments explained here includes High Temperature Gate Bias (HTGB), Switching Cycling, Power Cycling, and Thermal Cycling. These experiments stress different failure mechanisms, that show degradation in different device parameters including, but not limited to, threshold voltage and on-resistance. These four experiments help illustrate the spectrum between device and package degradation that can be used to design more reliable power electronic circuits.

AB - Integrating SiC power MOSFETs is very attractive for advancing power electronic system performance, yet the system reliability with new devices remains in question. This work presents an overview of accelerated lifetime tests and the packaging and semiconductor failure mechanisms they excite. The experiments explained here includes High Temperature Gate Bias (HTGB), Switching Cycling, Power Cycling, and Thermal Cycling. These experiments stress different failure mechanisms, that show degradation in different device parameters including, but not limited to, threshold voltage and on-resistance. These four experiments help illustrate the spectrum between device and package degradation that can be used to design more reliable power electronic circuits.

KW - Accelerated Testing

KW - MOSFET

KW - Reliability

KW - Silicon Carbide

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ER -

Impact of Accelerated Stress-Tests on SiC MOSFET Precursor Parameters

Abstract

Conference

Bibliographical note

NREL Publication Number

Keywords

Access to Document

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