Impact of Accelerated StressTests on SiC MOSFET Precursor Parameters: Preprint

Douglas DeVoto, Joshua Major, Joseph Kozak, Khai Ngo

Research output: Contribution to conferencePaper

Abstract

Incorporating SiC power MOSFETs is very attractive for advancing power electronic system performance, yet the system reliability with new devices remains in question. This work presents an overview of accelerated lifetime tests and the packaging and semiconductor failure mechanisms they excite. The experiments explained here includes High Temperature Gate Bias (HTGB), Switching Cycling, Power Cycling, and Thermal Cycling. These experiments stress different failure mechanisms, that show degradation in different device parameters including, but not limited to, threshold voltage and on-resistance. These four experiments help illustrate the spectrum between device and package degradation that can be used to design more reliable power electronic circuits.
Original languageAmerican English
Number of pages7
StatePublished - 2018
EventInternational Symposium on 3D Power Electronics Integration and Manufacturing (3D PEIM) - College Park, Maryland
Duration: 25 Jun 201827 Jun 2018

Conference

ConferenceInternational Symposium on 3D Power Electronics Integration and Manufacturing (3D PEIM)
CityCollege Park, Maryland
Period25/06/1827/06/18

Bibliographical note

See NREL/CP-5400-73008 for paper as published in IEEE proceedings

NREL Publication Number

  • NREL/CP-5400-71331

Keywords

  • accelerated testing
  • MOSFET
  • reliability
  • silicon carbide

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