Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All 'Room Temperature' Ion Implantations

Stephen Mancini; Seung Jang; Zeyu Chen; Dongyoung Kim; Alex Bialy; Balaji Raghotamacher; Michael Dudley; Nadeemullah Mahadik; Robert Stahlbush; Mowafak Al-Jassim; Woongje Sung

doi:10.1109/JEDS.2024.3359974

Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All 'Room Temperature' Ion Implantations

Stephen Mancini, Seung Jang, Zeyu Chen, Dongyoung Kim, Alex Bialy, Balaji Raghotamacher, Michael Dudley, Nadeemullah Mahadik, Robert Stahlbush, Mowafak Al-Jassim, Woongje Sung

Materials Science

Research output: Contribution to journal › Article › peer-review

1 Scopus Citations

Abstract

Several different designs of 1.2kV-rated 4H-SiC MOSFETs have been successfully fabricated under various ion implantation conditions. Implantation conditions consisted of different P+ profiles and implantation temperatures of both room temperature (25 degrees C) and elevated temperatures (600 degrees C) in order to monitor subsequent lattice damage. Through the use of X-Ray topography, SEM imaging, and electrical measurements, it was shown that room temperature implanted devices can mimic the static performances of high temperature implanted MOSFETs and reduce lattice damage suffered during the fabrication process, when the dose of high energy implants are suppressed.

Original language	American English
Pages (from-to)	150-158
Number of pages	9
Journal	IEEE Journal of the Electron Devices Society
Volume	12
DOIs	https://doi.org/10.1109/JEDS.2024.3359974
State	Published - 2024

NREL Publication Number

NREL/JA-5K00-89005

Keywords

3rd quadrant
4H-silicon carbide (SiC)
breakdown voltage
design approach
leakage current
MOSFET
room temperature implantation
SEM-analysis
X-ray topography

Access to Document

10.1109/JEDS.2024.3359974

https://www.nrel.gov/docs/fy24osti/89005.pdf

Cite this

@article{ad8c60615d83467da6c4e538927dbe4e,

title = "Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All 'Room Temperature' Ion Implantations",

abstract = "Several different designs of 1.2kV-rated 4H-SiC MOSFETs have been successfully fabricated under various ion implantation conditions. Implantation conditions consisted of different P+ profiles and implantation temperatures of both room temperature (25 degrees C) and elevated temperatures (600 degrees C) in order to monitor subsequent lattice damage. Through the use of X-Ray topography, SEM imaging, and electrical measurements, it was shown that room temperature implanted devices can mimic the static performances of high temperature implanted MOSFETs and reduce lattice damage suffered during the fabrication process, when the dose of high energy implants are suppressed.",

keywords = "3rd quadrant, 4H-silicon carbide (SiC), breakdown voltage, design approach, leakage current, MOSFET, room temperature implantation, SEM-analysis, X-ray topography",

author = "Stephen Mancini and Seung Jang and Zeyu Chen and Dongyoung Kim and Alex Bialy and Balaji Raghotamacher and Michael Dudley and Nadeemullah Mahadik and Robert Stahlbush and Mowafak Al-Jassim and Woongje Sung",

year = "2024",

doi = "10.1109/JEDS.2024.3359974",

language = "American English",

volume = "12",

pages = "150--158",

journal = "IEEE Journal of the Electron Devices Society",

issn = "2168-6734",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All 'Room Temperature' Ion Implantations

AU - Mancini, Stephen

AU - Jang, Seung

AU - Chen, Zeyu

AU - Kim, Dongyoung

AU - Bialy, Alex

AU - Raghotamacher, Balaji

AU - Dudley, Michael

AU - Mahadik, Nadeemullah

AU - Stahlbush, Robert

AU - Al-Jassim, Mowafak

AU - Sung, Woongje

PY - 2024

Y1 - 2024

N2 - Several different designs of 1.2kV-rated 4H-SiC MOSFETs have been successfully fabricated under various ion implantation conditions. Implantation conditions consisted of different P+ profiles and implantation temperatures of both room temperature (25 degrees C) and elevated temperatures (600 degrees C) in order to monitor subsequent lattice damage. Through the use of X-Ray topography, SEM imaging, and electrical measurements, it was shown that room temperature implanted devices can mimic the static performances of high temperature implanted MOSFETs and reduce lattice damage suffered during the fabrication process, when the dose of high energy implants are suppressed.

AB - Several different designs of 1.2kV-rated 4H-SiC MOSFETs have been successfully fabricated under various ion implantation conditions. Implantation conditions consisted of different P+ profiles and implantation temperatures of both room temperature (25 degrees C) and elevated temperatures (600 degrees C) in order to monitor subsequent lattice damage. Through the use of X-Ray topography, SEM imaging, and electrical measurements, it was shown that room temperature implanted devices can mimic the static performances of high temperature implanted MOSFETs and reduce lattice damage suffered during the fabrication process, when the dose of high energy implants are suppressed.

KW - 3rd quadrant

KW - 4H-silicon carbide (SiC)

KW - breakdown voltage

KW - design approach

KW - leakage current

KW - MOSFET

KW - room temperature implantation

KW - SEM-analysis

KW - X-ray topography

U2 - 10.1109/JEDS.2024.3359974

DO - 10.1109/JEDS.2024.3359974

M3 - Article

SN - 2168-6734

VL - 12

SP - 150

EP - 158

JO - IEEE Journal of the Electron Devices Society

JF - IEEE Journal of the Electron Devices Society

ER -

Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All 'Room Temperature' Ion Implantations

Abstract

NREL Publication Number

Keywords

Access to Document

Fingerprint

Cite this