Abstract
Power hardware-in-the-loop (PHIL) simulation, where actual hardware under text is coupled with a real-time digital model in closed loop, is a powerful tool for analyzing new methods of control for emerging distributed power systems. However, without careful design and compensation of the interface between the simulated and actual systems, PHIL simulations may exhibit instability and modeling inaccuracies. This paper addresses issues that arise in the PHIL simulation of a hardware battery inverter interfaced with a simulated distribution feeder. Both the stability and accuracy issues are modeled and characterized, and a methodology for design of PHIL interface compensation to ensure stability and accuracy is presented. The stability and accuracy of the resulting compensated PHIL simulation is then shown by experiment.
Original language | American English |
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Number of pages | 8 |
State | Published - 2017 |
Event | 2016 North American Power Symposium (NAPS) - Denver, Colorado Duration: 18 Sep 2016 → 20 Sep 2016 |
Conference
Conference | 2016 North American Power Symposium (NAPS) |
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City | Denver, Colorado |
Period | 18/09/16 → 20/09/16 |
Bibliographical note
See NREL/CP-5D00-66520 for the paper as published in IEEE conference proceedingsNREL Publication Number
- NREL/CP-5D00-70263
Keywords
- power hardware-in-the-loop
- power system dynamics
- power system simulation
- stability analysis