Novel Power-Hardware-in-the-Loop Interface Method for Grid-Forming Inverter Systems

Soham Chakraborty, Jaesang Park, Govind Saraswat, Toby Meyers, Jing Wang, Soumya Tiwari, Atif Maqsood, Apurva Somani, Murti Salapaka

Research output: Contribution to conferencePaperpeer-review

4 Scopus Citations

Abstract

Power-hardware-in-the-loop (PHIL) simulations of grid-forming (GFM) inverter systems facilitate the testing of drastic scenarios, such as on-grid to off-grid transitions and islanded microgrid operations without a stiff grid. To the authors' best knowledge, most studies in the literature focus on PHIL simulations for grid-following inverter systems. Only a few studies focus on GFM inverters, and those are challenging and problematic, especially for high-power applications. This article proposes a novel PHIL simulation platform that enables interfacing high-power GFM inverter systems. The paper proposes the concept of a virtual GFM inverter as a part of the proposed PHIL interface. This addition of a virtual GFM inverter in the PHIL interface expands the conventional ideal transformer model (ITM) method and enables it to overcome the issues of instability of existing ITM methods. In the validation stage, a PHIL experiment is conducted on a three-phase, 480-V, 125-kVA GFM inverter system with the proposed interfacing method. The results corroborate that the proposed PHIL simulation method performs well and is stable for GFM inverter systems.

Original languageAmerican English
Number of pages6
DOIs
StatePublished - 2022
Event48th Annual Conference of the IEEE Industrial Electronics Society, IECON 2022 - Brussels, Belgium
Duration: 17 Oct 202220 Oct 2022

Conference

Conference48th Annual Conference of the IEEE Industrial Electronics Society, IECON 2022
Country/TerritoryBelgium
CityBrussels
Period17/10/2220/10/22

Bibliographical note

See NREL/CP-5D00-82885 for preprint

NREL Publication Number

  • NREL/CP-5D00-85137

Keywords

  • Droop control
  • grid forming inverter
  • ITM-based interface method
  • power hardware-in-the-loop simulation

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