PHIL Interface Design for Use with a Voltage-Regulated Amplifier

Toby Meyers, Kumaraguru Prabakar, Annabelle Pratt, Soumya Tiwari, John Fossum

Research output: Contribution to conferencePaper


Power hardware-in-the-loop (PHIL) has emerged as a leading strategy to thoroughly assess the impact of proprietary inverter controls on a specific power system. The development of a PHIL test bed typically involves an inverter under test, a power amplifier, controllable DC supply, and a digital real-time simulator (DRTS) to simulate the power system under study. As a result of PHIL nonidealities, a form of digital compensation within the DRTS is used, which is commonly referred to as a PHIL interface. Many existing methods use legacy power amplifiers that do not contain internal voltage regulation. These existing interface methods are based around a voltage regulator within the DRTS and do not consider the interaction with the controls in newer amplifiers. In this study, a three-step approach of PHIL interface development for modern power amplifiers with built-in voltage regulation is introduced and is validated in hardware with a 30-kW grid-following inverter.
Original languageAmerican English
Number of pages5
StatePublished - 2023
Event2023 IEEE PES Innovative Smart Grid Technologies Latin American (ISGT-LA) - San Juan, Puerto Rico
Duration: 6 Nov 20239 Nov 2023


Conference2023 IEEE PES Innovative Smart Grid Technologies Latin American (ISGT-LA)
CitySan Juan, Puerto Rico

Bibliographical note

See NREL/CP-5D00-81369 for preprint

NREL Publication Number

  • NREL/CP-5D00-88562


  • inverter controls assessment
  • PHIL interface
  • PHIL stability
  • power hardware-in-the-loop
  • voltage-regulated power amplifier


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