PHIL Interface Design for Use With a Voltage-Regulated Amplifier: Preprint

Toby Meyers, Kumaraguru Prabakar, Annabelle Pratt, Soumya Tiwari, John Fossum

Research output: Contribution to conferencePaper


As inverter controls have become increasingly complex, power hardware-in-the-loop (PHIL) has emerged as a leading strategy to thoroughly assess the impact of proprietary inverter controls on a specific power system. The development of a PHIL test bed typically involves the desired inverter, a power amplifier, and a digital real-time simulator (DRTS) to control the simulated power system. As a result of PHIL nonidealities, a form of digital compensation within the DRTS is used, which is commonly referred to as a PHIL interface. The interface design for PHIL test beds has been previously examined in the literature, but many existing methods use older power amplifiers that do not contain internal voltage regulation. These existing interface methods are based around a voltage regulator within the DRTS rather than one preexisting in hardware. In this study, a three-step approach of PHIL interface development for modern power amplifiers with built-in voltage regulation is introduced and validated in hardware with a single 30-kW grid-following inverter.
Original languageAmerican English
Number of pages8
StatePublished - 2023
Event2023 IEEE PES Innovative Smart Grid Technologies Latin American (ISGT-LA) - San Juan, Puerto Rico
Duration: 6 Nov 20229 Nov 2022


Conference2023 IEEE PES Innovative Smart Grid Technologies Latin American (ISGT-LA)
CitySan Juan, Puerto Rico

Bibliographical note

See NREL/CP-5D00-88562 for paper as published in proceedings

NREL Publication Number

  • NREL/CP-5D00-81369


  • DRTS
  • grid-following inverter
  • illusionary reactive power
  • PHIL
  • PHIL interface
  • power hardware-in-the-loop
  • voltage-regulated power amplifier


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