Process Optimization for High Efficiency Heterojunction c-Si Solar Cells Fabrication Using Hot-Wire Chemical Vapor Deposition: Preprint

Process Optimization for High Efficiency Heterojunction c-Si Solar Cells Fabrication Using Hot-Wire Chemical Vapor Deposition: Preprint

Research output: Contribution to conference › Paper

Abstract

The researchers extensively studied the effects of annealing or thermal history of cell process on the minority carrier lifetimes of FZ n-type c-Si wafers with various i-layer thicknesses from 5 to 60 nm, substrate temperatures from 100 to 350 degrees C, doped layers both p- and n-types, and transparent conducting oxide (TCO).

Original language	American English
Number of pages	6
State	Published - 2012
Event	2012 IEEE Photovoltaic Specialists Conference - Austin, Texas Duration: 3 Jun 2012 → 8 Jun 2012

Conference

Conference	2012 IEEE Photovoltaic Specialists Conference
City	Austin, Texas
Period	3/06/12 → 8/06/12

NREL Publication Number

NREL/CP-5200-54099

Keywords

a-Si:H
c-Si
carrier lifetime
heterojunctions
passivation

Access to Document

https://www.nrel.gov/docs/fy12osti/54099.pdf

Cite this

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title = "Process Optimization for High Efficiency Heterojunction c-Si Solar Cells Fabrication Using Hot-Wire Chemical Vapor Deposition: Preprint",

abstract = "The researchers extensively studied the effects of annealing or thermal history of cell process on the minority carrier lifetimes of FZ n-type c-Si wafers with various i-layer thicknesses from 5 to 60 nm, substrate temperatures from 100 to 350 degrees C, doped layers both p- and n-types, and transparent conducting oxide (TCO).",

keywords = "a-Si:H, c-Si, carrier lifetime, heterojunctions, passivation",

author = "NREL",

year = "2012",

language = "American English",

note = "2012 IEEE Photovoltaic Specialists Conference ; Conference date: 03-06-2012 Through 08-06-2012",

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TY - CONF

T1 - Process Optimization for High Efficiency Heterojunction c-Si Solar Cells Fabrication Using Hot-Wire Chemical Vapor Deposition: Preprint

AU - NREL, null

PY - 2012

Y1 - 2012

N2 - The researchers extensively studied the effects of annealing or thermal history of cell process on the minority carrier lifetimes of FZ n-type c-Si wafers with various i-layer thicknesses from 5 to 60 nm, substrate temperatures from 100 to 350 degrees C, doped layers both p- and n-types, and transparent conducting oxide (TCO).

AB - The researchers extensively studied the effects of annealing or thermal history of cell process on the minority carrier lifetimes of FZ n-type c-Si wafers with various i-layer thicknesses from 5 to 60 nm, substrate temperatures from 100 to 350 degrees C, doped layers both p- and n-types, and transparent conducting oxide (TCO).

KW - a-Si:H

KW - c-Si

KW - carrier lifetime

KW - heterojunctions

KW - passivation

M3 - Paper

T2 - 2012 IEEE Photovoltaic Specialists Conference

Y2 - 3 June 2012 through 8 June 2012

ER -

Process Optimization for High Efficiency Heterojunction c-Si Solar Cells Fabrication Using Hot-Wire Chemical Vapor Deposition: Preprint

Abstract

Conference

NREL Publication Number

Keywords

Access to Document

Fingerprint

Cite this