Process Optimization for High Efficiency Heterojunction c-Si Solar Cells Fabrication Using Hot-Wire Chemical Vapor Deposition: Preprint

Research output: Contribution to conferencePaper

Abstract

The researchers extensively studied the effects of annealing or thermal history of cell process on the minority carrier lifetimes of FZ n-type c-Si wafers with various i-layer thicknesses from 5 to 60 nm, substrate temperatures from 100 to 350 degrees C, doped layers both p- and n-types, and transparent conducting oxide (TCO).
Original languageAmerican English
Number of pages6
StatePublished - 2012
Event2012 IEEE Photovoltaic Specialists Conference - Austin, Texas
Duration: 3 Jun 20128 Jun 2012

Conference

Conference2012 IEEE Photovoltaic Specialists Conference
CityAustin, Texas
Period3/06/128/06/12

NREL Publication Number

  • NREL/CP-5200-54099

Keywords

  • a-Si:H
  • c-Si
  • carrier lifetime
  • heterojunctions
  • passivation

Fingerprint

Dive into the research topics of 'Process Optimization for High Efficiency Heterojunction c-Si Solar Cells Fabrication Using Hot-Wire Chemical Vapor Deposition: Preprint'. Together they form a unique fingerprint.

Cite this