Process Optimization for High Efficiency Heterojunction c-Si Solar Cells Fabrication Using Hot-Wire Chemical Vapor Deposition

The researchers extensively studied the effects of annealing or thermal history of cell process on the minority carrier lifetimes of FZ n-type c-Si wafers with various i-layer thicknesses from 5 to 60 nm, substrate temperatures from 100 to 350°C, doped layers both p- and n-types, and transparent conducting oxide (TCO). Hot-Wire Chemical Vapor Deposition (HW-CVD) was used to achieve high lifetime, high open circuit voltage (V_oc), and high efficiency in crystalline silicon (c-Si) heterojunction (HJ) solar cells. The minority carrier lifetime with i-layer passivation in as-grown state was found to peak at 200°C substrate temperature. Annealing c-Si with as-grown layers affects the lifetime significantly. The optimized annealing temperature is from 250-350°C. It was also found that the lifetime of c-Si wafers with a very thin i/p passivation decreases significantly when annealed at temperatures higher than 250°C. However, the lifetime of the i/p passivated c-Si wafers is not affected by the p-layer even when the i-layer is as thin as 10 nm. Fourier Transform Infrared Spectroscopy (FTIR) was used to understand the annealing effect. For the c-Si wafers with i/n passivation, the minority carrier lifetime is usually longer than 2 ms and slightly improved by annealing. Minority carrier lifetime greater than 1 ms in a double side HJ structure with i/n and i/p layers can be achieved by controlling thermal history of the cell process. HJ cells were fabricated with an efficiency >18% on n-type wafers without texturing, and an efficiency of 19.2% with texturing.